The present invention relates generally to circuits of the type fabricated on a monolithic silicon semiconductor chip employing insulated-gate field-effect transistors (IGFETs) and, more particularly, to a five-transistor latch cell which can be fabricated employing complementary metal-oxide-semiconductor (CMOS) transistor technology and which can be employed to form various types of static flip-flops having low transistor counts.
One form of flip-flop useful in digital logic applications is a D-type master-slave flip-flop, also known as an edge-triggered D-type flip-flop. Such a flip-flop has a data input (D input), either one or a pair of complementary data outputs (Q or Q or both), and a clock input. In operation, a logic state is retained or latched at the output or outputs indefinitely so long as the clock level remains either high (binary "1") or low (binary "0"). Data in the form of a logic level is transferred to the data output (Q output) upon a specified clock pulse edge or transition, for example, a transition of the clock input from logic low to logic high. If provided, complementary data is available at the Q output.
Typically, a plurality of such D-type, master-slave flip-flops are included in a single integrated circuit. As one example, such flip-flops are available in packages of two flip-flop circuits formed on a monolithic silicon semiconductor chip and included in a single integrated circuit package. A specific example of such an integrated circuit, commercially available is an RCA Type No. CD4013 "Dual `D`-Type Flip-Flop". As another example, a plurality of such D-type master-slave flip-flops can be connected in series to form a static shift register. Example of such static shift registers, commercially available in integrated circuit form, are an RCA Type No. CD4015 "COS/MOS Dual Four-Stage Static Shift Register", which comprises two four-stage shift registers available in a single integrated circuit package, and an RCA Type No. CD4006 "COS/MOS 18-Stage Static Shift Register". In another form, such flip-flops may be included as but a small part of a much larger integrated circuit (e.g. large scale integration), in combination with either a variety of other types of digital logic elements and circuits comprising a functional device.
In either case, the integrated circuit typically includes a number of other elements supporting the flip-flop circuit. These other elements include at least voltage supply lines or nodes. Also, typical D-type, master-slave flip-flops require complementary clock inputs (e.g. CLK and CLK) and a pair of inverters will typically be included, common to a number of individual D-type master-slave flip-flops to provide complementary clock inputs.
As implied by the name of such a flip-flop, each flip-flop comprises two sections, known in the art as a "master" section and a "slave" section, respectively. Each of the sections may also be viewed as an inverting latch cell. One general type of prior art inverting latch cell typical of CMOS digital logic implementation comprises a CMOS transmission gate at the cell input supplying a pair of cross-coupled CMOS inverters, one of which may be termed a "forward-going" inverter because its output is connected to the cell output, and the other of which may be termed a "reverse-going" inverter. In the cross-coupled configuration, the output of one inverter is connected to the input of the other inverter, and the output of the other inverter is connected to the input of the one inverter through a standard CMOS transmission gate. A standard CMOS transmission gate includes a complementary pair of IGFETs, and a standard CMOS inverter also includes a complementary pair of IGFETs. Thus, each inverting latch cell or flip-flop section includes eight IGFETs, for a total of sixteen IGFETs in the overall D-type master-slave flip-flop.
To form an edge-triggered D-type flip-flop, the two inverting latch cells are connected in series, with the clock inputs connected to the two transmission gates such that the transmission gates are alternately enabled. Typically, the transmission gate of the first or "master" section is enabled when the clock input is low, and the transmission gate of the second or "slave" section is enabled when the clock input is high.
In general operation, with the clock input low, input data is passed via the master section transmission gate into the master section latch comprising a pair of cross-coupled inverters. When the clock input goes high, the transmission gate of the master section is no longer enabled, isolating the data input from the flip-flop. At the same time, the slave section transmission gate is enabled, coupling inverted data from the master section into the latch of the slave section, where the data appears at the outputs. When the clock goes low, the transmission gate of the slave section is no longer enabled, isolating the slave section from the rest of the flip-flop, and the slave section accordingly retains the output logic voltage levels until a subsequent low to high clock transition.
In the design of integrated circuits, particularly large scale integrated circuits comprising a multiplicity of individual logic elements, important considerations are minimizing the transistor count and reducing the circuit area required for each individual logic element or circuit.
In general, transistor count can be minimized through choice of circuit configuration. One particular approach is to eliminate the need for transmission gates as identifiable elements by employing modified CMOS inverters which include isolation diodes appropriately connected such that the inverters are capable of being selectively enabled or disabled depending upon the sense of the supply voltage polarity applied thereto. The inverter voltage supply nodes, rather than being connected to constantly-energized voltage supply lines, are connected to the complementary clock inputs, CLK and CLK. Thus, a particular inverter is either enabled or disabled depending upon the clock input. When such an inverter is disabled, its output impedance is quite high, to the extent that the inverter output is essentially an open circuit with respect to either logic voltage level. Specific examples of such modified CMOS inverter circuits, capable of being selectively enabled or disabled, are disclosed in Heuner et al U.S. Pat. No. 3,716,723 and Parrish et al U.S. Pat. No. 3,716,724.
However, latch circuits employing these modified CMOS inverter circuits heavily load the clock inputs, tending to slow circuit operation.